VLSI Academy - Signal Integrity
MP4 | Video: 804x480 | 63 kbps | 44 KHz | Duration: 7 Hours | 405 MB
Real and practical steps to build chip with minimum Signal Integrity issues
Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.
Crosstalk is the interference caused due to communication between the circuits
Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
Reasons for Crosstalk
Introduction to Noise Margin
Crosstalk Glitch Example
Factors Affecting Glitch Height
AC Noise Margin
Timing Window Concepts
Impact of Crosstalk on Setup and Hold Timing
Techniques to reduce Crosstalk
Power Supply Noise
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